Job Responsibilities:

• Perform logic design, RTL coding, design verification, logic synthesis, DFT and static timing analysis.
• Carry out module-level or top-level functional verification using software and FPGA prototype board.
• Interface with back-end ASIC design team for physical implementation.
• Prepare technical documents.

Requirements:

• Bachelor or above in Electronic Engineering or equivalent. Higher degree would be considered as an advantage.
• Knowledge of programming FPGA to verify IC design.
• Knowledge of using Design Compiler is preferable.
• Knowledge of scripting languages such as Perl, TCL and Makefile is preferable.
• Hands-on experience in Verilog-based logic design and synthesis is preferable.
• Team player and strong communication/documentation skills.
• Fresh graduate will also be considered.

Apply via inquiry@visharetech.com