I applied online. I interviewed at Intel Corporation (Hillsboro, OR) in Oct 2018
Interview
One screening phone call and 6 on campus rounds including hr round
Verilog, architecture, power, timing, circuit and hr at intel oregon campus
Interviewed at CPU design team. Offered physical design position.
I applied in-person. The process took 1 day. I interviewed at Intel Corporation (Santa Clarita, CA) in Jan 2016
Interview
Got selected for a screening interview after an in-person interaction at an info session. After one screening interview, got a call for an on-site after 2 months. It was a full day grilling interview @ Santa Clara, CA. There were four rounds - 3 technical and 1 behavioral.
First round was behavioral,
then next round was logic design/comp arch mixed,
next purely digital logic design,
and last one was purely comp arch.
Interview questions [3]
Question 1
Describe a situation when you would use a Direct mapped cache over a set associative cache.
Draw a state diagram for a given pattern. If even number if 0's come as input, then the output is asserted on every even consecutive 1.
If odd number if 0's come as input, then the output is asserted on every odd consecutive 1.
I applied through an employee referral. The process took 4 weeks. I interviewed at Intel Corporation in Dec 2015
Interview
Applied through employee referral program. Cleared Phone Interview and was called for on-site. Phone Interview: It was a very easy interview. Basics of computer architecture and programming were asked. On-site Interview: It was a four round interview. Mainly focused on the resume, logic design and programming skills. Also had a behavioural round. Interview experience was quite good.
Interview questions [1]
Question 1
Many questions are framed out of my resume in almost all rounds.
