Cirrus Logic Entry Level Design Verification Engineer Interview Questions

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Entry Level Design Verification Engineer Interview

19 Feb 2016

Anonymous interview candidate

No offer

Negative experience

Easy interview

Application

I applied online. The process took 1 week. I interviewed at Cirrus Logic (Dallas, TX) in Feb 2016

Interview

I had applied for the position in December. Got a call in February. I had prepared for more detailed SystemVerilog questions, but the phone interview was mostly basic and application-oriented - DSP, analog, OOPs concepts, and verification fundamentals. The interviewer was satisfied with most of my answers. I thought it went well. They didn't apparently. Got a reject in 2 days.

Interview questions [2]

Question 1

For a six-deep FIFO with one (and two clocks), push and pop operations, what specific test cases will you use to verify the design?

Answer question

Question 2

What is the difference between using a struct in C and an object in C++?

1 Answer

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Entry Level Design Verification Engineer Interview

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Entry Level Design Verification Engineer Interview