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      Capgemini Engineering

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      ASIC Design Verification Engineer Interview

      17 Sept 2021
      Anonymous interview candidate
      New Delhi
      Declined offer
      Positive experience
      Average interview

      Application

      The process took 4 weeks. I interviewed at Capgemini Engineering (New Delhi)

      Interview

      The 1st round was a 3 hour test. Where they check basics of verilog, system verilog and UVM 2nd round was called the 1st technical round where there is a face to face interview. And they'll ask you basics and the AMBA protocols which you know. 3rd round is called the 2nd technical interview where there will ba a face to face interview and again they'll ask you about the projects you completed and explanation of those projects. 4th round is the HR round where the HR will ask you basic questions about your background and stuff. Please note that there will be a 3 year bond. And the bond breakage amount is 6.75 Lakhs. (For 3 years) Overall the interview was reasonably hard and all the interviews were very professional.

      Interview questions [5]

      Question 1

      program for pattern detector for FSM
      Answer question

      Question 2

      program for ring counter and Johnson counter in verilog
      Answer question

      Question 3

      show how code coverage and function coverage works. explain with code
      Answer question

      Question 4

      write code for generating clock of 50MHz frequency, with 5% jitter and duty cycle.
      Answer question

      Question 5

      APB and AXI protocol explation with all signals.
      Answer question
      1

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